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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MCM6343
256K x 16 Bit 3.3 V Asynchronous Fast Static RAM
The MCM6343 is a 4,194,304-bit static random access memory organized as 262,144 words of 16 bits. Static design eliminates the need for external clocks or timing strobes. The MCM6343 is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Separate byte enable controls (LB and UB) allow individual bytes to be written and read. LB controls the lower bits DQ0 to DQ7, while UB controls the upper bits DQ8 to DQ15. The MCM6343 is available in a 400 mil, 44-lead small-outline SOJ package and a 44-lead TSOP Type II package. * * * * * * * * Single 3.3 V 0.3 V Power Supply Fast Access Time: 12/15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Data Byte Control Fully Static Operation Power Operation: 250/240/230 mA Maximum, Active AC Commercial and Standard Industrial Temperature Option: - 40 to + 85C BLOCK DIAGRAM
G OUTPUT ENABLE BUFFER 9 A 18 ADDRESS BUFFERS 9 ROW COLUMN DECODER DECODER 8 HIGH BYTE OUTPUT ENABLE LOW BYTE OUTPUT ENABLE 8 HIGH BYTE OUTPUT BUFFER HIGH BYTE WRITE DRIVER 8 YJ PACKAGE 400 MIL SOJ CASE 919-01 TS PACKAGE TSOP TYPE II CASE 924A-02
PIN ASSIGNMENT
A A A A A E DQ0 DQ1 DQ2 DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 W A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A A A G UB LB DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 DQ9 DQ8 NC A A A A A
E
CHIP ENABLE BUFFER 256K x 16 BIT MEMORY ARRAY 16 SENSE AMPS 8
8
W
WRITE ENABLE BUFFER
LOW BYTE OUTPUT BUFFER 8 LOW BYTE WRITE DRIVER
8
A
PIN NAMES
8 A0 - A17 . . . . . . . . . . . . . . . . . Address Input E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable W . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte DQ0 - DQ15 . . . . . . . . . . Data Input/Output VDD . . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connection
LB UB
BYTE ENABLE BUFFER
HIGH BYTE WRITE ENABLE LOW BYTE WRITE ENABLE
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 2 2/10/98
(c) Motorola, Inc. 1998 MOTOROLA FAST SRAM
MCM6343 1
TRUTH TABLE (X = Don't Care)
E H L L L L L L L L G X H X L L L X X X W X H X H H H L L L LB X X H L H L L H L UB X X H H L L H L L Mode Not Selected Output Disabled Output Disabled Low Byte Read High Byte Read Word Read Low Byte Write High Byte Write Word Write VDD Current ISB1, ISB2 IDDA IDDA IDDA IDDA IDDA IDDA IDDA IDDA DQ0 - DQ7 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din DQ8 - DQ15 High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
ABSOLUTE MAXIMUM RATINGS (See Notes)
Rating Supply Voltage Voltage on Any Pin Output Current per Pin Package Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Commercial Industrial Commercial Industrial Symbol VDD Vin Iout PD Tbias TA Tstg Value - 0.5 to + 4.6 - 0.5 to VDD + 0.5 20 TBD - 10 to + 85 - 45 to + 90 0 to + 70 - 45 to + 85 - 55 to + 150 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability will be dependent upon package characteristics and use environment.
MCM6343 2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 0.3 V, TA = 0 to 70C, Unless Otherwise Noted) (TA = - 40 to + 85C for Industrial Temperature Offering) RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD VIH VIL Min 3.0 2.2 - 0.5* Typ 3.3 -- -- Max 3.6 VDD + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (E = VIH, Vout = 0 to VDD) Output Low Voltage Output High Voltage (IOL = + 4.0 mA) (IOL = + 100 A) (IOH = - 4.0 mA) (IOH = - 100 A) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 VDD - 0.2 Max 1.0 1.0 0.4 VSS + 0.2 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VCC = max) AC Standby Current (VCC = max, E = VIH, No other restrictions on other inputs) MCM6343-12: tAVAV = 12 ns MCM6343-15: tAVAV = 15 ns MCM6343-12: tAVAV = 12 ns MCM6343-15: tAVAV = 15 ns Symbol ICC ISB1 ISB2 0 to 70C 240 230 50 45 5 - 40 to + 85C 240 55 50 5 Unit mA mA mA
CMOS Standby Current (E VCC - 0.2 V, Vin VSS + 0.2 V or VCC - 0.2 V) (VCC = max, f = 0 MHz)
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Address Input Capacitance Control Input Capacitance Input/Output Capacitance Symbol Cin Cin CI/O Typ -- -- -- Max 6 6 8 Unit pF pF pF
MOTOROLA FAST SRAM
MCM6343 3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V 0.3 V, TA = 0 to + 70C, Unless Otherwise Noted) (TA = - 40 to + 85C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level . . . . . . . . 1.50 V Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM6343-12 Parameter P Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable Low to Output Active Enable High to Output High-Z Output Enable High to Output High-Z Byte Enable Access Time Byte Enable Low to Output Active Byte High to Output High-Z Symbol S bl tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ tBLQV tBLQX tBHQZ Min 12 -- -- -- 3 3 0 0 0 -- 0 0 Max -- 12 12 6 -- -- -- 6 6 6 -- 6 MCM6343-15 Min 15 -- -- -- 3 3 0 0 0 -- 0 0 Max -- 15 15 7 -- -- -- 7 7 7 -- 7 Unit Ui ns ns ns ns ns ns ns ns ns ns ns ns 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 5 Notes N 4
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. Device is continuously selected (E VIL, G VIL). 4. All read cycle timings are referenced from the last valid address to the first transitioning address. 5. Addresses valid prior to or coincident with E going low. 6. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device to device. 7. This parameter is sampled and not 100% tested. 8. Transition is measured 200 mV from steady-state voltage.
t
t
TIMING LIMITS
RL = 50 OUTPUT Z0 = 50 VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1. AC Test Load
MCM6343 4
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 8)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 4)
tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX LB, UB (BYTE ENABLE) tBLQV tBLQX Q (DATA OUT) DATA VALID tBHQZ tGHQZ tEHQZ
MOTOROLA FAST SRAM
MCM6343 5
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
MCM6343-12 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Write Pulse Width Write Pulse Width (G High) Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol S bl tAVAV tAVWL tAVWH tAVWH tWLWH tWLEH tWLWH tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 12 0 10 9 10 9 6 0 0 3 0 Max -- -- -- -- -- -- -- -- 6 -- -- MCM6343-15 Min 15 0 12 10 12 10 7 0 0 3 0 Max -- -- -- -- -- -- -- -- 7 -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 Notes N 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. 5. This parameter is sampled and not 100% tested. 6. Transition is measured 200 mV from steady-state voltage. 7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL LB, UB (BYTE ENABLE) tDVWH D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tWHQX DATA VALID tWHDX tWHAX
MCM6343 6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
MCM6343-12 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Enable to End of Write Enable to End of Write (G High) Data Valid to End of Write Data Hold Time Write Recovery Time Symbol S bl tAVAV tAVEL tAVEH tAVEH tELEH, tELWH tELEH, tELWH tDVEH tEHDX tEHAX Min 12 0 10 9 10 9 6 0 0 Max -- -- -- -- -- -- -- -- -- MCM6343-15 Min 15 0 12 10 12 10 7 0 0 Max -- -- -- -- -- -- -- -- -- Unit Ui ns ns ns ns ns ns ns ns ns 5, 6 5, 6 Notes N 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes low coincident with or after W goes low, the output will remain in a high-impedance condition. 6. If E goes high coincident with or before W goes high, the output will remain in a high-impedance condition.
WRITE CYCLE 2
(E Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tELWH tEHAX
LB, UB (BYTE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX
Q (DATA OUT)
HIGH-Z
MOTOROLA FAST SRAM
MCM6343 7
WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3)
MCM6343-12 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Byte Pulse Width Byte Pulse Width (G High) Data Valid to End of Write Data Hold Time Symbol S bl tAVAV tAVBL tAVBH tAVBH tBLWH tBLEH tBLWH tBLEH tDVBH tBHDX Min 12 0 10 9 10 9 6 0 Max -- -- -- -- -- -- -- -- MCM6343-15 Min 15 0 12 10 12 10 7 0 Max -- -- -- -- -- -- -- -- Unit Ui ns ns ns ns ns ns ns ns Notes N 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address.
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVBH E (CHIP ENABLE) tAVBL LB, UB (BYTE ENABLE) tBHDX W (WRITE ENABLE) tDVBH D (DATA IN) DATA VALID tBLEH tBLWH
Q (DATA OUT)
HIGH-Z
HIGH-Z
MCM6343 8
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number) XCM
Motorola Memory Prefix Part Number
6943
XX
XX
X
Shipping Method (R = Tape and Reel, Blank = Rails) Speed (12 = 12 ns, 15 = 15 ns) Package (YJ = 400 mil SOJ, TS = TSOP Type II)
Full Commercial Part Numbers -- MCM6343YJ12 MCM6343YJ15 Full Industrial Part Numbers -- SCM6343YJ12A SCM6343YJ15A * Not available in Tape and Reel.
MCM6343YJ12R MCM6343YJ15R SCM6343YJ12AR SCM6343YJ15AR
MCM6343TS12 MCM6343TS15 SCM6343TS12A* SCM6343TS15A*
PACKAGE DIMENSIONS
YJ PACKAGE 44-LEAD 400 MIL SOJ CASE 919-01
44 23 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, TIE BAR BURRS AND GATE BURRS. MOLD FLASH, TIE BAR BURRS AND GATE BURRS SHALL NOT EXCEED 0.006 PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010 PER SIDE. 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 AND, HENCE, DATUMS A AND B, ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 5. DIMENSION b1 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b1 MAX BY MORE THAN 0.005. THE DAMBAR INTRUSION(S) SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001 BELOW b1 MIN. INCHES MIN MAX 0.128 0.148 0.025 --- 0.082 --- 0.035 0.045 0.015 0.020 0.026 0.032 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC 0.030 0.040
E1
1
22
B A D
44X b1 42X
e
0.007
L
CAB A
A3
SEATING PLANE
e /2 C
44X
A 0.004 C
b
M
0.007
CAB
DIM A A1 A2 A3 b b1 D E E1 E2 e R1
E A A2
44X R
0.007
M
CAB
R1
A1 0.015 B
22 ZONES 2X
E2 /2 E2 VIEW A-A
MOTOROLA FAST SRAM
MCM6343 9
TS PACKAGE 44-LEAD TSOP TYPE II CASE 924A-02 B
44 23
VIEW A
E1 AA
1
22
A2 A A
22X
D
0.2
M
E CB
44X
0.004 (0.1) C
SEATING PLANE 4X
e /2
42X
e
C
NOTES: 1. DIMENSIONINS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. 4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58. DIM A A1 A2 b c D e E E1 L MILLIMETERS MIN MAX --- 1.20 0.05 0.15 0.95 1.05 0.30 0.45 0.12 0.21 18.28 18.54 0.80 BSC 11.56 11.96 10.03 10.29 0.40 0.60 0_ 5_
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
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MCM6343 10
EEEE EEEE EEEE
b 0.2
M
c A1 L VIEW A ROTATED 90 _ CLOCKWISE
CB
SECTION A-A
40 PLACES
q
q
MCM6343/D MOTOROLA FAST SRAM

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